Novel ASIC Design flow for Multi-rate FIR Filter from System Specification to Functional Verification

Finite impulse response filter holds important part in DSP designs. Multi-rate FIR filters specially are the integral part of the various DSP applications like speech coding, audio compression, image processing and others. In VLSI designs, especially nowadays, in SOC designs, requires efficient implementation of FIR filter. Fixed point FIR filter design is the challenging task in ASIC designs. Here, ASIC design flow for a multi-rate FIR filter is proposed from system parameters to verification. From the help of FDATOOL in MATLAB, different fixed point FIR filters are designed and RTL like MATLAB model is designed. Also, filter coefficients are optimized with common sub expression elimination technique. This model helps in optimizing HDL modeling in terms of arithmetic and verification.